1. Field of the Invention
This invention generally relates to the provision of synchronous clock pulses to multiple, distributed devices. More specifically, the invention relates to methods and systems that are particularly well suited for providing high frequency synchronous clock pulses to multiple portions of a computer or digital electronic processing system.
2. Prior Art
There are many applications for clock distribution in computer systems, including the transmit and receive byte clock on a digital communication link (either copper or optical), the transmission of a clock signal along with multiple data channels in a parallel optical link with DC coupled receivers (as used in a self-timed interface or similar control bus). Indeed, this concept applies to any level of a computer complex or data communications network, from clock distribution within chips and multichip modules, to distribution on cards and backplanes, to synchronous clocking over wide area networks that span many kilometers using wavelength multiplexing for optical transport. The common feature of all these approaches is that multiple clocks can be synchronized with each other to create multiprocessor clusters or parallel coupled systems, with local clock generation and recovery synchronized across the cluster such that any processor may run from any clock source with no discernable difference in performance. Various implementations of this are possible, including both digital and analog clocking schemes.
The performance and correct operation of complex digital circuits or computer complexes is critically dependent upon the timing of the signals propagated through them; often there are many possible signaling paths through a complex system, each with its own unique timing requirements.
For this reason, the operation of digital circuits is periodically reclocked at intervals known as the cycle time. The cycle time is usually determined by a system clock which produces clock signals of different phases to allow for signal propagation and settling times, to assure that all signals are in the intended logic state when the various digital circuits are permitted to respond to these inputs. Since the cycle times must accommodate all propagation delays and other signal distortion and settling times within the system, the clock cycle must often accommodate the largest delay in the system. The cycle time thus imposes this delay on the entire system and limits the operational speed.
For the same reasons, the key to improving system speed has been to reduce the propagation times of the individual elements in a digital circuit. This approach has been successfully implemented in many conventional designs, resulting in cycle times on the order of 1 to 10 nanoseconds (clock rates of 100 MHz to several GHz). A problem is encountered in the distribution of clock signals since they must be propagated throughout the entire system to maintain synchronization, as opposed to simply clocking a few circuits on a single chip or module where the signals may be more easily regenerated over path lengths of only a few inches. Longer system clock signal paths are subject to noise and distortion, and may include connections which accentuate these effects; such as line termination impedance mismatch in an electrical clock distribution tree. Commonly, the prior art attempts to correct for differential time delays with variations in designs of “deskewing” and buffering or tapped delay-line circuits.
Noise and delay are, therefore, minimized by designing the system master oscillator to run at the lowest frequency permitted by synchronous distribution. In other words, local high speed clocks must receive a synchronizing signal from some source at some minimal interval depending on the required clock precision. Conversely, for a given precision of synchronization, the minimum frequency of the synchronization signal must be increased with an increasing local, high speed clock rate. Difficulties begin to arise with clock or synchronization frequencies above around 100 MHz; using fiber optic technology, clock signals can now be increased into the multi-GHz range or beyond. Use of fiber optic methods is the only practical way to overcome limitations on electrical systems imposed by parasitic capacitance and other reactive electrical characteristics, which often cannot be precisely predicted or modeled at higher frequencies.